现代电子技术2017，Vol.40Issue(17)：44-46,50,4.DOI:10.16652/j.issn.1004-373x.2017.17.011
基于FPGA的图像超分辨率的硬件化实现
FPGA-based hardware implementation of image super-resolution
摘要
Abstract
An FPGA-based implementation mode of image super-resolution bilinear interpolation was designed. A two-stage round-robin scheduling mechanism based on RAM with single-input and dual-output port is proposed to realize the shared re-source allocation and parallel pipeline processing. RAM with single-input and dual-output port can read two data whose address are adjacent. The quantity of pixels within a row in source image is deemed as the depth of RAM,and the width of pixel data is deemed as that of RAM to store the two rows of pixels adjacent to the source data. The position of source image is gotten according to the position analysis module. The data of source image is written into the corresponding RAM for weighting operation. In order to improve the efficiency,the ping-pong algorithm is adopted to design four RAMs which are divided into two groups(each one includes two RAMs). If one group of RAMs is performed with weighting calculation,another group of RAMs is performed with data write-in. The design was verified on Kintex-7 development board,which can process the image with the speed of 25～30 f/s. The interpolated image has clear detail. The image is equalized,which is shown in histogram.关键词
FPGA/超分辨率/双线性插值/循环调度Key words
FPGA/super-resolution/bilinear interpolation/round-robin scheduling分类
信息技术与安全科学引用本文复制引用
钟雪燕,夏前亮,陈智军..基于FPGA的图像超分辨率的硬件化实现[J].现代电子技术,2017,40(17):44-46,50,4.基金项目
国家自然科学基金面上项目(51475240) （51475240）
航空科学基金自由探索类项目(2014ZD52053) （2014ZD52053）
江苏省轨道交通控制工程技术研究开发中心开放基金(KFJ1509) （KFJ1509）
