现代电子技术2017，Vol.40Issue(16)：148-150,3.DOI:10.16652/j.issn.1004-373x.2017.16.043
改进型CIC抽取滤波器的FPGA实现
FPGA-based implementation of modified CIC decimation filter
摘要
Abstract
In order to reduce the data rate and power consumption of the previously-designed CIC decimation filter,the FPGA-based realization process of the improved CIC decimation filter is studied,the hardware implementation structure of the CIC decimation filter is optimized,and FPGA is used to design the decimation filter.The hardware implementation structure and bit wide of CIC decimation filter are analyzed.The filter structure is decimated through Hogenauer to get the CIC hardware implementation structure whose decimation rate is 16 and decimation degree is 6.The structure is transformed into four cascaded CIC decimation filters implemented with FPGA,which can reduce the data rate and improve the data bit wide.In the implementation process of CIC decimation filter with FPGA,the highest bit wide required by the register while it is operating is analyzed to avoid the data overflow problem.The experimental result shows that the modified CIC decimation filter is effective,and can reduce the data rate and system power consumption.关键词
Hogenauer/CIC抽取滤波器/数据速率/FPGAKey words
Hogenauer/CIC decimation filter/data rate/FPGA分类
信息技术与安全科学引用本文复制引用
谢海霞,赵欣..改进型CIC抽取滤波器的FPGA实现[J].现代电子技术,2017,40(16):148-150,3.基金项目
国家自然科学基金(10701031) （10701031）
海南省自然科学基金资助(20166224) （20166224）
琼州学院实践教改项目(QYSJ2013-001) （QYSJ2013-001）
