计算机与数字工程2017，Vol.45Issue(9)：1866-1869,1887,5.DOI:10.3969/j.issn.1672-9722.2017.09.037
基于FPGA的甚低频宽带接收机设计
Design of VLF Wideband Receiver Based on FPGA
摘要
Abstract
In VLF communication technology,the research of VLF receiver is of great significance. A VLF receiver based on FPGA is proposed in this paper. The design,implementation and verification of the system are given. 10kHz~50kHz signal filtering, gain adjustment,sampling and DDC processing functions are mainly achieved. The data is transmitted to the computer through the Ethernet interface for signal demodulation and analysis. The working mode of the VLF receiving and collecting processing module can be set up by the instruction,and the output mode of the DDC mode or the direct sampling filter is provided. The receiver can cheaply obtain the standard time signal accurately,with good scalability,hign bandwidth,high reliability,carrying easyly,etc. It provides a feasible technical scheme for the detection of VLF signal.关键词
甚低频/宽带/接收机/FPGAKey words
VLF/wideband/receiver/FPGA分类
信息技术与安全科学引用本文复制引用
张驰,芮国胜,王瑞,薛鹏..基于FPGA的甚低频宽带接收机设计[J].计算机与数字工程,2017,45(9):1866-1869,1887,5.基金项目
国家自然科学基金项目(编号:41606117,41476089,61671016)资助. （编号:41606117,41476089,61671016）
