电子器件2017，Vol.40Issue(5)：1104-1107,4.DOI:10.3969/j.issn.1005-9490.2017.05.011
一种基于FPGA的多通道复用鉴相器的设计与实现
Design and Implementation of a Multi-Channel Multiplexed Phase Detector Based on FPGA
张秀清 1康亚楠 2刘岩 2王晓君2
作者信息
- 1. 河北工业大学电气工程学院,天津300130
- 2. 河北科技大学信息科学与工程学院,石家庄050000
- 折叠
摘要
Abstract
For the problem of more resource consumption and production costs of multi-channel phase detector in the navigation receiver, a multi-channel multiplexed phase detector based on FPGA is proposed. The multi-channel related results are arbitrated and cached by the arbitration unit and FIFO buffer. The multi-channel parallel data is transformed into single-channel serial data to send to FIFO,which send the serial data to the phase detector,and the same phase detector is used to calculate and process by multi-channel. The number of phase detector is decreased seriously to only one in the tracking loop,and resource consumption and production costs are saved correspondingly.关键词
多通道鉴相器/资源占用/生产成本/通道复用/仲裁单元/FIFOKey words
multi-channel phase detector/resource consumption/production cost/channel multiplexing/arbitration unit/FIFO分类
信息技术与安全科学引用本文复制引用
张秀清,康亚楠,刘岩,王晓君..一种基于FPGA的多通道复用鉴相器的设计与实现[J].电子器件,2017,40(5):1104-1107,4.
