计算机工程与应用2017，Vol.53Issue(21)：58-61,4.DOI:10.3778/j.issn.1002-8331.1606-0358
基于FPGA的进位存储大数乘法器的改进与实现
Improvement and implementation of carry-save large numbers multiplication on FPGA
摘要
Abstract
This paper proposes an improved algorithm of carry-save large numbers multiplication on FPGA, which can complete multiple iterations of operation in a clock with a serial-parallel hybrid structure. To some extent, reducing clocks to complete a operation, the structure improves the speed of the large numbers multiplication effectively. Finally, the results of the implementation of this multiplier for several operands sizes(192 bit, 256 bit, 384 bit)on Altera Stratix II EP2S90F1508C3 show that the time of 192 bit is 0.185 microsecond , 256 bit is 0.271 microsecond, and 384 bit is 0.595 microsecond. As a result, the paper's design is about 3.5 times than the previous design in speed.关键词
大数乘法/串并混合结构/多次迭代/现场可编程门阵列Key words
large numbers multiplication/serial-parallel hybrid structure/multiple iterations/Field Programmable Gate Array(FPGA)分类
信息技术与安全科学引用本文复制引用
张晓楠,高献伟,董秀则..基于FPGA的进位存储大数乘法器的改进与实现[J].计算机工程与应用,2017,53(21):58-61,4.基金项目
北京市自然科学基金(No.4163076) （No.4163076）
北京电子科技学院校内科研基金(No.2014TD1-DXZ). （No.2014TD1-DXZ）
