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适用于超宽带系统的低功耗CMOS频率合成器研究

李建伟

电子器件2017,Vol.40Issue(6):1348-1353,6.
电子器件2017,Vol.40Issue(6):1348-1353,6.DOI:10.3969/j.issn.1005-9490.2017.06.004

适用于超宽带系统的低功耗CMOS频率合成器研究

Research on Low Power CMOS Frequency Synthesizer for Ultra Wide Band System

李建伟1

作者信息

  • 1. 长治学院电子信息与物理系,山西 长治046000
  • 折叠

摘要

Abstract

A low power frequency synthesizer design is proposed for the impulse radio ultra wideband( IR-UWB) re-ceiving system. The synthesizer is designed on the basis of an integer N frequency divisionⅡtype four order phase locked loop structure,which includes a 7 bit voltage controlled oscillator with a tuning range of 31%,and a set of high speed frequency divider based on single phase clock logic. The frequency divider is capable of synthesizing eight frequencies defined by the IEEE standard 802. 15. 4a. The integrated frequency synthesizer is made with 65 CMOS nm technology,with an area of 0.33 mm2 and a working frequency range of 7.5 GHz~10.6 GHz. Test results show that under the 1.2 V power supply,the synthesizer's 3-dB closed loop bandwidth is 100 kHz,and the stability time is 15. Measured phase noise is less than dBc/Hz@1 MHz-103,the offset frequency is 1 MHz. The spurious signal power is below dBc-58. Compared to other advanced synthesizer,the synthesizer's operating current is 5.13 mA,the power consumption is only 6.23 mW.

关键词

超宽带/锁相环路/频率合成器/低功耗/相位噪声

Key words

ultra wide band/phase locked loop/frequency synthesizer/low power consumption/phase noise

分类

信息技术与安全科学

引用本文复制引用

李建伟..适用于超宽带系统的低功耗CMOS频率合成器研究[J].电子器件,2017,40(6):1348-1353,6.

基金项目

长治学院校级科学研究项目( 2013203) ( 2013203)

电子器件

OA北大核心CSTPCD

1005-9490

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