半导体学报（英文版）2017，Vol.38Issue(12)：13-21,9.DOI:10.1088/1674-4926/38/12/122002
Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length
Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length
Neeraj Jain 1Balwinder Raj1
作者信息
- 1. VLSI Design Lab, Department of Electronics and Communication Engineering, Dr.B.R.Ambedkar National Institute of Technology(NIT), Jalandhar, India
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摘要
关键词
SOI FinFET/SCEs/underlap region/DIBL/analog and RF performanceKey words
SOI FinFET/SCEs/underlap region/DIBL/analog and RF performance引用本文复制引用
Neeraj Jain,Balwinder Raj..Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length[J].半导体学报（英文版）,2017,38(12):13-21,9.
