桂林电子科技大学学报2017，Vol.37Issue(5)：372-377,6.
一种用于产生高频八相位时钟的延时锁定环
A delay-locked loop for generating high speed eight phases clock
摘要
Abstract
In order to conquer the weakness of low operation frequency and narrow lock range of the conventional DLL,a de-lay-locked loop (DLL)for generating high speed eight phases clock is implemented.A high frequency phase frequency detec-tor (PFD)with eight transistors is proposed.It decreases jitter and dead zone by not using reset path.Fast differential cas-code voltage-switch-logic(DCVSL)-based voltage control delay cell is adopted to satisfy requirement of wide range delay for solving mismatch of rising delay and falling delay through resistance correction.A shunt control element is employed to fulfil the second time control of voltage control delay line (VCDL),expands operation frequency and solves false lock as well as harmonic lock.The proposed DLL,which is capable of generating eight phases clock,is implemented in SMIC 0.18 μm CMOS process,a chip area is 0.03 mm2 ,a reference frequency range is 1.8-4.5 GHz.At maximum input frequency,the proposed DLL has a jitter of 3.2 ps and dissipates 54 mW power.关键词
延时锁定环/多相时钟/鉴相器/压控延时单元Key words
DLL/multiphase clock/PFD/voltage control delay cell分类
信息技术与安全科学引用本文复制引用
鲜卓霖,段吉海,朱智勇,赵洪飞..一种用于产生高频八相位时钟的延时锁定环[J].桂林电子科技大学学报,2017,37(5):372-377,6.基金项目
国家自然科学基金(61161003,61264001,61166004) （61161003,61264001,61166004）
广西精密导航技术与应用重点实验室基金(DH201501) （DH201501）
