自动化学报2017，Vol.43Issue(12)：2225-2231,7.DOI:10.16383/j.aas.2017.c160162
一种超低相位噪声频率合成源方案设计
A Ultralow-phase-noise Scheme for Frequency Synthesizer
摘要
Abstract
Frequency synthesizer is one of the most important component of RF generator and spectrum analysis. The performance of its output signal is evaluated in terms of phase noise, scattering, frequency resolution and frequency hopping time. By analyzing the traditional theory of phase-locked loop, a ultralow-phase-noise scheme for the frequency synthesizer is put forward (bandwidth within 100 MHz). In order to make the frequency resolution of the output signal reach to 0.1 mHz in theory and optimize the in-band phase noise cver 17 dB, direct digital synthesizer (DDS) and mixer phase detection technology based on phase-locked loop are introduced. Consideration is also given to both scattering and frequency hopping time to ensure the output signal is stable and reliable. The synthesizer has a good application in the field of automatic test.关键词
频率合成源/锁相环/极高分辨率/超低相位噪声Key words
Frequency synthesizer/phase-locked loop/high resolution/ultralow phase noise引用本文复制引用
王李飞,张宁,彭子健,薛沛祥,李维亮..一种超低相位噪声频率合成源方案设计[J].自动化学报,2017,43(12):2225-2231,7.基金项目
电子测试技术重点实验室基金项目(9140C120201130C12050)资助Supported by Project of Science and Technology on Electronic Test & （9140C120201130C12050）
Measurement Laboratory(9140C120201130C12050) （9140C120201130C12050）
