国防科技大学学报2017，Vol.39Issue(6)：39-44,6.DOI:10.11887/j.cn.201706007
用于DDR3访存优化的数据缓冲机制
DDR3 data buffering for memory access optimization
摘要
Abstract
In order to improve the memory access efficiency of the DDR3 memory controller,a data buffering mechanism based on DDR3 memory access burst length was proposed.The application requests were guided into three different queues.The data buffering mechanism can make use of the additional data obtained from DRAM(dynamic random access memory) in one of the former request,thus reducing the actual external DRAM access needed.Experiments on several image and video application show that the proposed mechanism can improve the memory controller by an average 21.3％ and a peak by 51.3％ at an acceptable hardware cost when compared with the FCFS ( first-come-first-serve) baseline DDR3 memory controller.关键词
DDR3控制器/访存优化/数据缓冲Key words
DDR3 memory controller/memory access optimization/data buffering分类
信息技术与安全科学引用本文复制引用
陈胜刚,付兴飞,曾思,刘胜..用于DDR3访存优化的数据缓冲机制[J].国防科技大学学报,2017,39(6):39-44,6.基金项目
国家自然科学基金资助项目(61402499,61602493,61402500,61672526) （61402499,61602493,61402500,61672526）
