计算机工程与科学2018，Vol.40Issue(1)：24-33,10.DOI:10.3969/j.issn.1007-130X.2018.01.004
容错处理器阵列的多逻辑列并行重构算法
A parallel multiple logical columns reconfiguration algorithm on fault-tolerant processor arrays
摘要
Abstract
Efficient fault-tolerant reconfiguration techniques are essential for improving the reliability of high performance architecture such as mesh-connected processor arrays.Meanwhile,reconfiguration must be achieved as fast as possible to meet the real-time constraints.Existing techniques of generating maximum logic array on parallel reconfiguration are only for the single logical column,and no maximum logic array algorithm is reported for reconfiguring multi-logical columns in parallel on processor arrays.According to the potential parallelism of mesh-connected processor arrays,based on the divide and conquer strategy,this paper proposes a parallel algorithm to reconstruct the logical array.The proposed algorithm divides processors array into subarrays,then reconfigures each subarray in parallel.After that,it merges the logical subarrays in parallel.The proposed algorithm can effectively accelerate the running speed by reducing the data redundancy in communication and calculation.Moreover,it is proved that the proposed algorithm can generate the maximum logic array.Experimental results show that the proposed algorithm is faster by nearly 39.6％ than the existing parallel algorithm on a 64× 64 processor array and has good scalability.关键词
处理器阵列/重构/容错/并行算法Key words
processor arrays/reconfiguration/fault-tolerant/parallel algorithm分类
信息技术与安全科学引用本文复制引用
章子凯,武继刚,姜文超,刘竹松..容错处理器阵列的多逻辑列并行重构算法[J].计算机工程与科学,2018,40(1):24-33,10.基金项目
国家自然科学基金(61572144,61672171) （61572144,61672171）
广东省科技计划应用专项基金(2015B010129014) （2015B010129014）
广东省自然科学基金(2016A030313703) （2016A030313703）
