单片机与嵌入式系统应用2018，Vol.18Issue(3)：52-55,4.
双FIFO的LBE总线与Avalon总线的接口系统设计
Design of Interface System Between LBE Bus and Avalon Bus Based on Two FIFOs
苗军民 1史志钊 1吕迎迎1
作者信息
- 1. 中航工业洛阳电光设备研究所,洛阳 471000
- 折叠
摘要
Abstract
In order to achieve the cross-clock domain data exchange between devices with LBE bus and Avalon bus,the interface IP soft core connected between the two buses is designed.The Verilog hardware is used to describe the hierarchical design method of language. The interface IP core module is designed,which including command FIFO module,state FIFO module,LBE interface module and Avalon interface module.In the FPGA hardware platform,two-way data transmission experiment between two buses is carried out.The results show that the interface system with two FIFOs between LBE bus and Avalon bus can exchange data steadily and reliably.关键词
FIFO/LBE总线/Avalon总线/IP软核Key words
FIFO/LBE bus/Avalon bus/IP soft core分类
信息技术与安全科学引用本文复制引用
苗军民,史志钊,吕迎迎..双FIFO的LBE总线与Avalon总线的接口系统设计[J].单片机与嵌入式系统应用,2018,18(3):52-55,4.
