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基于单计算单元的极化码CA-SCL译码器FPGA设计

魏一鸣仰枫帆

计算机与数字工程2018，Vol.46Issue(2)：391-396,6.

计算机与数字工程2018，Vol.46Issue(2)：391-396,6.DOI:10.3969/j.issn.1672-9722.2018.02.036

基于单计算单元的极化码CA-SCL译码器FPGA设计

Design on SCL Decoder of Polar Code Based on FPGA

魏一鸣 ¹仰枫帆¹

作者信息

1. 南京航空航天大学电子信息工程学院南京211106
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摘要

Abstract

In recent years,polar code is a hot topic in the field of channel coding,and many researchers start paying attention to hardware implementation.Nowadays,CA-SCL decoding algorithm is widely regarded as the algorithm that can achieve good per-formance. In order to improve the parallelism of CA-SCL decoding algorithm,a method is proposed to associate every candidate path with a SC decoding core containing many processing elements,which consumes a large amount of hardware resources.To han-dle this case,an architecture is proposed in which every decoding path associate with only one processing element,which greatly re-duces the system area.The design is synthesized for a blocklength of N=1024 bits,code rate 1/2 and list size L=32 using Strtix V de-vice of Alter,Inc.When the clock frequency is 300MHz,the decoding throughput can be up to 6.24Mbps,meanwhile,the hard-ware utilization is only 6%.

关键词

极化码/SCL译码算法/单计算单元/FPGA

Key words

polar code/SCL decoding algorithm/single processing element/FPGA

分类

信息技术与安全科学

引用本文复制引用

魏一鸣,仰枫帆..基于单计算单元的极化码CA-SCL译码器FPGA设计[J].计算机与数字工程,2018,46(2):391-396,6.

计算机与数字工程

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ISSN：1672-9722

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