计算机应用与软件2017，Vol.34Issue(12)：178-183,6.DOI:10.3969/j.issn.1000-386x.2017.12.034
基于有限状态机的高速串口通信收发器的FPGA设计
FPGA DESIGN FOR HIGH SPEED SERIAL COMMUNICATION TRANSCEIVER BASED ON FINITE STATE MACHINE
摘要
Abstract
Under the environment of multitask operating system,the character of real-time and high speed of serial communication is significantly affected.This article puts forward an FPGA implementation method of high speed serial communication transceiver based on finite state machine.The serial communication transceiver consists of four modules,baud rate generator,transmission module,reception module and control and status module.The baud rate generator uses a phase-locked loop to multiply and divide the input clock.The reception module and the transmission module use a finite state machine of four states and two states,respectively.Simulation and experimental results show that the FPGA serial transceiver module circuit works stably with the speed up to 3 Mbit/s.Due to the high parallelism of FPGA and the stability of finite state machine,the FPGA high speed serial communication transceiver based on finite state machine can guarantee the real-time and reliability of high speed serial communication in industrial applications.关键词
有限状态机/高速串行通信/收发器/FPGAKey words
Finite state machine/High speed serial communication/Transceiver/FPGA分类
信息技术与安全科学引用本文复制引用
陈孟春,冯建文..基于有限状态机的高速串口通信收发器的FPGA设计[J].计算机应用与软件,2017,34(12):178-183,6.基金项目
国家自然科学基金项目(61471150). （61471150）
