西北师范大学学报（自然科学版）2018，Vol.54Issue(2)：121-126,6.DOI:10.16783/j.cnki.nwnuz.2018.02.021
一种高性能电荷泵锁相环电路的设计与实现
Design and implementation of a high performance charge-pump phase locked loop
摘要
Abstract
A charge-pump phase locked loop(PLL)is designed,which adopted 2/3 divider circuit,timing phase detector,charge-pump of differential input-single output,multilevel ring VCO,and external PLL loop filter.The PLL is fabricated in SMIC 0.18 μm CMOS technology.The simulation results of Hspice show that the achieved PLL can be used as a programmable frequency multiplier,and its adjustable range is wide.When the PLL locks,the control voltage is almost constant,the designed PLL has met the requirements,which can be applied in frequency synthesizer.关键词
电荷泵/频率合成器/鉴频鉴相器/锁相环Key words
charge-pump/frequency- synthesizer/phase-frequency detector(PFD)/phase locked loop (PLL)分类
信息技术与安全科学引用本文复制引用
唐玉兰,陈建慧,赵吉..一种高性能电荷泵锁相环电路的设计与实现[J].西北师范大学学报（自然科学版）,2018,54(2):121-126,6.基金项目
国家自然科学基金资助项目(61300149) （61300149）
江苏省博士后科研资助计划资助项目(1501138B) （1501138B）
无锡市教育科学"十二五"规划资助项目(J/D/2014/020) （J/D/2014/020）
