北京大学学报（自然科学版）2018，Vol.54Issue(2)：315-319,5.DOI:10.13209/j.0479-8023.2017.140
一种低资源数字抽取滤波器设计
Low Resource Consumption Design of Digital Decimation Filter
摘要
Abstract
A digital decimation filter applied to audio Sigma-Delta ADC is designed. The filter adopts the design of multi-stage and multi-rate down sampling structure, in-band ripple of decimation filter is less than 0.06 dB overall, bandwidth is 21.6 kHz, minimum working frequency is 10 MHz. Through the innovation of filter hardware architecture design, it effectively reduces the filter circuit area and power consumption. Chip test results show that the SNR is above 87.2 dB when processing PDM signals is at the down sampling rate of 64, 4 order Sigma-Delta modulation. Designed in SMIC's 0.13 μm CMOS process, the decimation filter area is 0.146 mm2. Filter area is reduced by 58%, and power consumption is reduced by over 60% compared with the same type decimation filters.关键词
抽取滤波器/Sigma-Delta/小面积/低功耗Key words
decimation filter/Sigma-Delta/small area/low power consumption分类
信息技术与安全科学引用本文复制引用
钱泽斌,严伟..一种低资源数字抽取滤波器设计[J].北京大学学报（自然科学版）,2018,54(2):315-319,5.基金项目
国家重点研发计划(2016YFC0801001)资助 （2016YFC0801001）
