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Modeling and nonlinear analysis of 14 bit 100MS/s pipelined ADC

Zheng Hao Fan Xiangning

高技术通讯（英文版）2018，Vol.24Issue(1)：36-45,10.

高技术通讯（英文版）2018，Vol.24Issue(1)：36-45,10.DOI:10.3772/j.issn.1006-6748.2018.01.005

Zheng Hao ¹Fan Xiangning¹

作者信息

1. Institute of RF&OE-ICs,School of Information Science and Engineering,Southeast University,Nanjing 210096,P.R.China
折叠

capacitor mismatch/offset/clock jitter/flip-around sample and hold(S/H)/second-order response

capacitor mismatch/offset/clock jitter/flip-around sample and hold(S/H)/second-order response

Zheng Hao,Fan Xiangning..Modeling and nonlinear analysis of 14 bit 100MS/s pipelined ADC[J].高技术通讯（英文版）,2018,24(1):36-45,10.

Supported by the National Basic Research Program of China(No.2010CB327404). （No.2010CB327404）

OAEI

ISSN：1006-6748

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