雷达科学与技术2018，Vol.16Issue(1)：68-72,86,6.DOI:10.3969/j.issn.1672-2337.2018.01.011
宽带分数抽取数字下变频设计
Design of Wideband Fractional Decimation Digital Down Conversion
王利华1
作者信息
- 1. 中国航空工业集团公司雷华电子技术研究所,江苏无锡214063
- 折叠
摘要
Abstract
In the wideband receiving system of radar,digital intermediate frequency (IF) sampling rate is limited by the overall design of the radio frequency system.The baseband signal data rate required by the signal processing system maybe not be obtained through integer decimation of the IF sampled signal.Considering the high sampling rate of wideband system,the parallel polyphase filter algorithm structure of digital down conversion,the multiple parallel branches of baseband signal,and the constraint of field programmable gate array (FP-GA),the wideband signal fractional decimation is realized often by use of parallel polyphase algorithm.Based on the parallel multiple baseband signals of wideband digital down conversion,the fractional decimation of wideband signal can be realized through parallel polyphase interpolation filter and parallel polyphase decimation filter,without increasing the processing clock of FPGA.关键词
宽带数字下变频/分数抽取/多相滤波/现场可编程门阵列Key words
wideband digital down conversion/fractional decimation/polyphase filter/field programmable gate array(FPGA)分类
信息技术与安全科学引用本文复制引用
王利华..宽带分数抽取数字下变频设计[J].雷达科学与技术,2018,16(1):68-72,86,6.
