太赫兹科学与电子信息学报2018，Vol.16Issue(1)：170-175,6.DOI:10.11805/TKYDA201801.0170
FIR基于FPGA的高并行度DA结构
FPGA based high parallelism DA architecture for FIR
摘要
Abstract
Finite Impulse Response(FIR) is an important component in Synthetic Aperture Radar (SAR) signal processing system. Considering both of the resource and performance impact for system, based on FPGA(Field Programmable Gate Array), a SAR signal processing FIR is designed with width and order of filter configurable. By comparing DA(Distributed Arithmetic) architectures with the meaningful address width of ROM(Read Only Memory) and different input parallelism, and analyzing the throughput-resource ratio of different architectures, the best high parallelism DA architecture is obtained. Experimental results show that throughput-resource ratio is best when address width of ROM is 4 or 5;and the throughput-resource ratio increases when input parallelism increases, and when input parallelism equals to input data width, throughput-resource ratio is improved by 24%-117%. Compared to traditional fully parallel architecture, fully serial architecture and DA architecture, optimized DA architecture can improve the throughput-resource ratio by 3 110%, 76% and 86%, respectively.关键词
现场可编程门阵列/有限长单位冲击响应滤波器/分布式算法(DA)/并行度/分块Key words
Field Programmable Gate Array(FPGA)/Finite Impulse Response(FIR)/Distributed Arithmetic(DA)/parallelism/partition分类
信息技术与安全科学引用本文复制引用
林跃杉,林郁,尹韬,黄志洪,杨海钢..FIR基于FPGA的高并行度DA结构[J].太赫兹科学与电子信息学报,2018,16(1):170-175,6.基金项目
国家自然科学基金资助项目(61474120,61271149,61404140) （61474120,61271149,61404140）
国家重点基础研究发展计划资助项目(2014CB744600) （2014CB744600）
