电子学报2017，Vol.45Issue(12)：2890-2895,6.DOI:10.3969/j.issn.0372-2112.2017.12.009
采用环型运放的12-bit40-MS/s采样保持电路设计实现
Implementation of a 12-bit 40-MS/s Sample-and-Hold Circuit with a Ring Amplifier
摘要
Abstract
In order to keep the analog to digital converter' s speed and precision,a sample-and-hold (S/H) circuit for a 12-bit 40-MS/s pipeline ADC is designed and fabricated using a 0.18 micrometer process.The proposed amplifier can simplify the design and occupies smaller area.The substrate bias effect of the switch transistor used in the bootstrapped switch can be eliminated with the silicon-on-insulator (SOI) process,which can increase the linearity of bootstrapped switch and improve the performance of the S/H circuit.The S/H circuit occupies an area of 0.023 square millimeter.Measurement results show that the S/H circuit operates at a 1.5 V supply and consumes 3.5mW,and the spurious free dynamic range is 76.85 dB for a 1 MHz input signal with 40 MS/s sampling rate.The S/H circuit meets the requirement of the 12-bit 40-MS/s pipeline analog to digital converter.关键词
采样保持电路/绝缘体上硅工艺/运放/栅压自举开关/无杂散动态范围Key words
S/H circuit/SOI process/amplifier/bootstrapped switch/SFDR分类
矿业与冶金引用本文复制引用
魏子辉,黄水龙,单强..采用环型运放的12-bit40-MS/s采样保持电路设计实现[J].电子学报,2017,45(12):2890-2895,6.基金项目
国家科技重大专项(No.2014ZX02302007) （No.2014ZX02302007）
青年科学基金(No.61404166) （No.61404166）
