高技术通讯2018，Vol.28Issue(2)：91-99,9.DOI:10.3772/j.issn.1002-0470.2018.02.001
基于自适应时序匹配的低延迟寄存器堆
A low latency register file based on adjustable access latency
摘要
Abstract
It is pointed that the random variation of the characteristic parameters of semiconductor process and transistors gets bigger with the decrease of the chip feature size,thus the traditional register file design based on prematch has to increase the matching margin to ensure the reliability of read and write operations.To overcome this key factor of restricting register file performance,a low power register file circuit structure based on adjustable access latency is proposed.The proposed mechanism can auto-test the practical path delay of the sense amplifier,and automatically match and tune time delay of sense enable signals to guarantee the correct operation,so as to improve the perform-ance and power of the circuit by reducing unnecessary margin pre-placed in design.For 3-read ports and 2-write ports 32×64bit register file generated in SMIC 40nm technology,its area is 135.5μm×65.1μm and read access latency is 357ps.The simulation results show that compared with the traditional chain delay technique,the read ac-cess latency and the power consumption of the mechanism are reduced by 22%and 35%respectively.关键词
多端口寄存器堆/自适应时序匹配/低延迟/低功耗/静态随机存储器Key words
multi-port register file/adjustable access latency/low latency/low power/static random access memory(SRAM)引用本文复制引用
元国军,沈华,邵恩,臧大伟..基于自适应时序匹配的低延迟寄存器堆[J].高技术通讯,2018,28(2):91-99,9.基金项目
国家自然科学基金(61572464,61331008)和十三五国家重点研发计划(2016YFB0200205)资助项目. （61572464,61331008）
