高技术通讯2018，Vol.28Issue(2)：111-120,10.DOI:10.3772/j.issn.1002-0470.2018.02.003
片上网络与系统域网络的协同设计探索
Co-design of on-chip networks and system interconnection networks
摘要
Abstract
It is pointed that to further improve network performance,integrating network devices into processors becomes an important trend,but with the increase of the on-chip processor number and the number of interchip interconnec-ted ports required by high dimensional system interconnection networks,the traditional processor architecture,IBM Blue Gene/Q,for example,will face the problems of scalability,on-chip traffic balancing and intership access fair-ness,etc.In consideration of this,a method for co-design of on-chip networks and system interconnection networks is proposed,which on one hand,provides balanced and fair network service to processing cores by distributing net-work interfaces into the on-chip network,and on the other hand,solves the scalability issue and reduces processor implementation cost by avoiding using crossbar in the centralized router.This proposed cooperative design method is systematically investigated from three aspects of collaborative routing, collaborative deployment of network inter-faces,and collaborative parameter setting.Also,a case study on the network architecture of TMesh is conducted, and the performance and feasibility of the virtual router architecture are analyzed.关键词
高性能计算(HPC)/片上网络/系统域互连网络/网络死锁/路由器Key words
high performance computing(HPC)/on-chip network/system interconnection network/dead-lock/router引用本文复制引用
刘小丽,郇志轩,曹政,孙凝晖..片上网络与系统域网络的协同设计探索[J].高技术通讯,2018,28(2):111-120,10.基金项目
国家重点研发计划(2016YFB0200204,2016YFB0200205),国家自然科学基金(61572464,61331008)和国家重点实验室开放课题基金(2016GZKF0JT006)资助项目. （2016YFB0200204,2016YFB0200205）
