电子器件2018，Vol.41Issue(3)：743-746,4.DOI:10.3969/j.issn.1005-9490.2018.03.038
基于FPGA的高速Fast-SSC译码器测试系统
High-Speed Fast-SSC Decoder Test System Based on FPGA
摘要
Abstract
To meet the demand for large amount of data during the high-performance test of polar code,a hardware test platform for Fast-SSC decoder is proposed on Altera Stratix V 5SGXEA7N2F45C2,which includes information source,encoder,modulation,channel model,demodulation,decoder and data statistics,and communicate with PC through PCIe interface. For a polar code of length 1024 and rate 1/2,results show that the decoding takes 19.18 s at a frequency of 300 MHz on test data with 1.4×1010 bit.关键词
测试平台/FPGA/Polar码/Fast-SSC译码器Key words
test platform/FPGA/polar code/Fast-SSC decoder分类
信息技术与安全科学引用本文复制引用
盛瑞平,张小军,张德学,高健,董雁飞..基于FPGA的高速Fast-SSC译码器测试系统[J].电子器件,2018,41(3):743-746,4.基金项目
中国博士后科学基金项目( 2016M592216) （ 2016M592216）
青岛市博士后应用研究项目( 2016125) （ 2016125）
