计算机工程与科学2018，Vol.40Issue(3)：388-393,6.DOI:10.3969/j.issn.1007-130X.2018.03.002
一款面向高性能SOC应用的高精度全数字锁相环设计
A novel high-resolution ADPLL for high-performance SOC application
赵信 1黄金明 1黄永勤 1胡向东1
作者信息
- 1. 上海高性能集成电路设计中心,上海210000
- 折叠
摘要
Abstract
Phase Locked Loop (PLL) is an essential part of high-performance SOCs that provide the chip with a system clock.This paper presents a novel All-Digital Phase-Locked Loop (ADPLL) structure for high-performance SOC applications and a novel high-resolution Time-to-Digital Converter (TDC) improves the phase detection precision and reduces the TDC phase noise and improves the PLL jitter performance.In the nanometer process,the ADPLL system is implemented by using digital standard cells,which solves the bottleneck problems such as poor portability to new process,big area of passive devices,and poor anti-noise ability in analog circuits.The system has the maximum frequency of 2.6GHz and the jitter performance less than 2 picoseconds.关键词
全数字锁相环/低抖动/时间数字转换器Key words
ADPLL/low jitter/TDC1分类
信息技术与安全科学引用本文复制引用
赵信,黄金明,黄永勤,胡向东..一款面向高性能SOC应用的高精度全数字锁相环设计[J].计算机工程与科学,2018,40(3):388-393,6.
