计算机工程与应用2018，Vol.54Issue(12)：57-62,6.DOI:10.3778/j.issn.1002-8331.1705-0436
视频阵列处理器多层次分布式存储结构设计
Design of distributed memory architecture for video array processor
摘要
Abstract
With the continuous development of video coding standards, the amount of data processed by video codec algo-rithm is also increasing sharply. Although the parallel processing technology of multi-core architecture promote the speed of processing of video codec algorithm, it makes the memory structure becomes the bottleneck of the whole codec system. Aiming at the characteristics of video codec algorithm of the locality accessing data, the high frequency of data exchange between different algorithm, a large number of temporary internal data does not need to interact, this paper designs and implements a multi level distributed storage structure which contains private storage layer and shared storage layer. The design has been tested on the FPGA development board of the company of Xilinx, the experimental results show that the structure not only maintain the simplicity and scalability, but also can provide data access bandwidth which can up to be 9.73 GB/s, meet the needs of video codec algorithm data access.关键词
视频阵列处理器/分布式存储结构/目录协议/高速缓存/层次化Key words
video array processor/distributed storage architecture/directory protocol/cache/hierarchical分类
信息技术与安全科学引用本文复制引用
蒋林,崔朋飞,山蕊,武鑫,田汝佳..视频阵列处理器多层次分布式存储结构设计[J].计算机工程与应用,2018,54(12):57-62,6.基金项目
国家自然科学基金(No.61272120,No.61634004,No.61602377) （No.61272120,No.61634004,No.61602377）
陕西省自然科学基金(No.2015JM6326) （No.2015JM6326）
陕西省科技统筹创新工程项目(No.2016KTZDGY02-04-02) （No.2016KTZDGY02-04-02）
陕西省教育厅自然科学研究项目(No.17JK0689). （No.17JK0689）
