西安电子科技大学学报（自然科学版）2018，Vol.45Issue(3)：91-96,6.DOI:10.3969/j.issn.1001-2400.2018.03.017
用于快速锁定全数字锁相环的反馈调节算法
Feedback tuning algorithm for fast-locking all-digital phase-locked loops
摘要
Abstract
An adaptable feedback tuning algorithm based on the analyses of various phase detection mechanisms and filter architectures is presented to shorten the locking time of all-digital phase-locked loops (ADPLLs).The algorithm divides the entire locking processes into coarse tuning,first fine tuning and second fine tuning processes corresponding to control codes of coarse,first and second fine stages in the digitally controlled oscillator (DCO).An appropriate filter architecture is chosen in each process while adaptive factors are tunable according to the value of the frequency error.A portable fast-locking fractional-N ADPLL based on the proposed algorithm is fabricated by 180 nm CMOS technology.Measurement shows that the average locking time is only 6.4μs,that is,128 reference cycles with a 20 MHz clock.The locking time is reduced by the algorithm effectively.关键词
频率调制/锁相环/全数字/快速锁定/反馈调节算法Key words
frequency modulation/phase locked loop/all digital/fast locking/feedback tuning algorithm分类
信息技术与安全科学引用本文复制引用
谢琳琳,王扬,乔树山,黑勇..用于快速锁定全数字锁相环的反馈调节算法[J].西安电子科技大学学报（自然科学版）,2018,45(3):91-96,6.基金项目
国家自然科学基金资助项目(61474135) （61474135）
