舰船电子工程2018，Vol.38Issue(6)：132-135,4.DOI:10.3969/j.issn.1672-9730.2018.06.034
一种高速低噪声的发散型时钟树结构
A High-speed Low-noise Divergent Clock Tree
吴雨臻 1袁书伟 1钟传杰1
作者信息
- 1. 江南大学物联网工程学院 无锡 214122
- 折叠
摘要
Abstract
Aiming at the characteristics of full-chip level(TOP level)in back-end design,such as huge area,lack of routing source,long clock route and large clock network noise,a high-speed low-noise divergent clock tree structure is proposed for the co?existence of blocks and flip-flops in full-chip level design,and a way to implement the clock tree is summarized. In the same de?sign,the proposed clock tree is compared with the traditional binary tree.The results show that the high-speed low-noise divergent clock tree has a 27 percent of reduction in clock latency,22 percent of reduction in clock skew and 59 percent of reduction in clock noise compared with the binary tree ,which greatly reduces the number of timing violations.关键词
时钟树综合/串扰噪声/时钟延时/时钟偏差/多级驱动Key words
clock tree synthesis/crosstalk noise/clock latency/clock skew/multi-driver分类
信息技术与安全科学引用本文复制引用
吴雨臻,袁书伟,钟传杰..一种高速低噪声的发散型时钟树结构[J].舰船电子工程,2018,38(6):132-135,4.
