信息与控制2018，Vol.47Issue(6)：713-721,729,10.DOI:10.13976/j.cnki.xk.2018.8086
一种面向WIA-PA系统级芯片的低功耗优化策略
A Low-power Optimization Strategy for WIA-PA System on Chip
摘要
Abstract
The wireless networks for industrial automation process automation (WIA-PA) system on chip (SoC) is the core component of WIA-PA wireless devices and occupies a large proportion of the total power consumption of the device. According to the application environment and working characteristics of WIA-PA devices, we study a variety of low-power optimization methods and propose a comprehensive low-power optimization strategy for WIA-PA SoC. The strategy combines multiple methods, e. g., gate control clock, asynchronous circuit application, system-level optimization, and process optimization. In addition, the strategy achieves both static and dynamic power consumption optimization by considering different circuit types and design levels. WIA-PA SoC has been completed for two times of type-out. The first time completes functional verification, whereas the second time realizes the proposed low-power optimization. We test the sample chips two times. Experimental data of power consumption reveal that the dynamic power consumption of the optimized sample chip is reduced by 71.2％ and the static power consumption is reduced by 99.5％. The comparison results demonstrate the effectiveness of the proposed optimization strategy.关键词
工业过程无线网络标准/系统级芯片/低功耗设计/时钟域/电源管理单元Key words
WIA-PAL/system on chip/low power design/clock domain/power manage unit分类
信息技术与安全科学引用本文复制引用
谢闯,杨志家,王剑..一种面向WIA-PA系统级芯片的低功耗优化策略[J].信息与控制,2018,47(6):713-721,729,10.基金项目
国家科技重大专项资助项目(2015ZX03003010) （2015ZX03003010）
