桂林电子科技大学学报2018，Vol.38Issue(6)：448-452,5.
基于FPGA的低硬件复杂度的极化码编码实现方案
FPGA implementation of low complexity polar code coding structure
摘要
Abstract
In order to reduce the cost of the polarization code encoding hardware circuit and improve the flexibility of the coding structure, an FPGA-based implementation of low-hardware complexity polarization code coding is proposed.The direct parallel Cronoke product operation structure with high hardware complexity in the polarization code coding is replaced by a multiplexing structure, and is encapsulated into an IP core capable of realizing any dimensional Kronecker product operation.The experimental results show that when the base matrix is second-order, the number of registers required to implement the minimum arithmetic unit is reduced to 1/4, and the overall hardware complexity is reduced to a linearity with the code length.关键词
极化码编码/克罗内克积/FPGA/面积优化Key words
polar code encoding/Kronecker product/FPGA/area optimized分类
信息技术与安全科学引用本文复制引用
周秉毅,陈紫强,谢跃雷,黄志成..基于FPGA的低硬件复杂度的极化码编码实现方案[J].桂林电子科技大学学报,2018,38(6):448-452,5.基金项目
国家自然科学基金(61461015) （61461015）
桂林电子科技大学研究生教育创新计划(2017YJCX24) （2017YJCX24）
