计算机工程与科学2018，Vol.40Issue(12)：2126-2132,7.DOI:10.3969/j.issn.1007-130X.2018.12.005
基于FPGA的HEVC后处理CNN硬件加速器研究
An FPGA-based HEVC post-processing CNN hardware accelerator
摘要
Abstract
Aiming at the shortcomings of the post-processing CNN algorithm running on the common platform according to the high-efficiency video code standard, we propose a post-processing convolutional neural network hardware parallel architecture based on field programmable gate array (FPGA) to improve the overall parallelism of the convolution module and the hardware flow of the module by optimizing the concurrent data input and output buffering process.Experiments on 176×144 video streams on the Xilinx ZCU102 show that the proposed CNN hardware accelerator can achieve an equivalent computational performance of 360.5 Gfloating-point operation per second.The computation speed can satisfy81.01 FPS, which is 76.67 times faster than that of the Intel i7-4790 Kwith a clock frequency of 4 Ghz.The speedup is 32.50 times faster than the NVIDIA GeForce GTX 750 Ti.In the calculation of energy efficiency ratio, the proposal's power consumption is 12.095 W, 512.9 times of that of the Intel i7-4790 Kand 125.78 times that of the NVIDIA GeForce GTX 750 Ti.关键词
高清视频编解码后处理/卷积神经网络/现场可编程逻辑门阵列/硬件实现Key words
HEVC post-processing/convolutional neural network/field programmable logic gate array (FPGA) /hardware implementation分类
信息技术与安全科学引用本文复制引用
夏珺,钱磊,严伟,柴志雷..基于FPGA的HEVC后处理CNN硬件加速器研究[J].计算机工程与科学,2018,40(12):2126-2132,7.基金项目
数学工程与先进计算国家重点实验室开放基金(2017A08) （2017A08）
国家重点研发计划(2016YFC0801001) （2016YFC0801001）
