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A 40 Gb/ s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology

Fangxu Lü Jianye Wang Xuqiang Zheng Ziqiang Wang Yajun He Hao Ding Yongcong Liu Chun Zhang Zhihua Wang

哈尔滨工业大学学报（英文版）2019，Vol.26Issue(3)：50-57,8.

哈尔滨工业大学学报（英文版）2019，Vol.26Issue(3)：50-57,8.DOI:10.11916/j.issn.1005-9113.17104

A 40 Gb/ s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology

Fangxu Lü ¹Jianye Wang ²Xuqiang Zheng ¹Ziqiang Wang ²Yajun He ²Hao Ding ²Yongcong Liu ¹Chun Zhang ¹Zhihua Wang²

作者信息

1. Air and Missile Defense College, Air Force Engineering University, Xi'an 710051, China
2. The Institute of Microelectronics, Tsinghua University, Beijing 100084, China
折叠

摘要

关键词

SerDes/transceiver/controller/PCS/PMA/CDR

Key words

SerDes/transceiver/controller/PCS/PMA/CDR

分类

信息技术与安全科学

引用本文复制引用

Fangxu Lü,Jianye Wang,Xuqiang Zheng,Ziqiang Wang,Yajun He,Hao Ding,Yongcong Liu,Chun Zhang,Zhihua Wang..A 40 Gb/ s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology[J].哈尔滨工业大学学报（英文版）,2019,26(3):50-57,8.

基金项目

Sponsored by the National Science Technology Major Project (Grant No. 2016ZX01012101). （Grant No. 2016ZX01012101）

哈尔滨工业大学学报（英文版）

ISSN：1005-9113

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