首页|期刊导航|半导体学报（英文版）|Reducing the power consumption of two-dimensional logic transistors

Reducing the power consumption of two-dimensional logic transistors

Weisheng Li Hongkai Ning Zhihao Yu Yi Shi Xinran Wang

半导体学报（英文版）2019，Vol.40Issue(9)：20-25,6.

半导体学报（英文版）2019，Vol.40Issue(9)：20-25,6.DOI:10.1088/1674-4926/40/9/091002

Reducing the power consumption of two-dimensional logic transistors

Weisheng Li ¹Hongkai Ning ¹Zhihao Yu ¹Yi Shi ¹Xinran Wang¹

作者信息

1. National Laboratory of Solid State Microstructures, School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China
折叠

摘要

关键词

2D materials/dielectric integration/interface/NCFETs/subthreshold slope/low power

Key words

2D materials/dielectric integration/interface/NCFETs/subthreshold slope/low power

引用本文复制引用

Weisheng Li,Hongkai Ning,Zhihao Yu,Yi Shi,Xinran Wang..Reducing the power consumption of two-dimensional logic transistors[J].半导体学报（英文版）,2019,40(9):20-25,6.

半导体学报（英文版）

OACSCDCSTPCD

ISSN：1674-4926

访问量0

下载量0

段落导航