测试科学与仪器2020，Vol.11Issue(3)：205-210,6.DOI:10.3969/j.issn.1674-8042.2020.03.001
基于改进型LFSR的低功耗MBIST地址生成器
An LFSR-based address generator using optimized address partition for low power memory BIST
摘要
Abstract
Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register (LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test (MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory (SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1％ and 68.2％, respectively,with low area overhead.关键词
地址序列/线性反馈移位寄存器/存储器内建自测试/地址生成器/翻转率Key words
address sequence/linear feedback shift register (LFSR)/memory built-in self-test (MBIST)/address generator/switching activity分类
信息技术与安全科学引用本文复制引用
虞致国,李青青,冯洋,顾晓峰..基于改进型LFSR的低功耗MBIST地址生成器[J].测试科学与仪器,2020,11(3):205-210,6.基金项目
Fundamental Research Funds for the Central Universities (No.JUSRP51510) （No.JUSRP51510）
Primary Research & Development Plan of Jiangsu Province (No.BE2019003-2) （No.BE2019003-2）
