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Large-Capacity and High-Speed Instruction Cache Based on Divide-by-2 Memory Banks

Qing-Qing Li Zhi-Guo Yu Yi Sun Jing-He Wei Xiao-Feng Gu

电子科技学刊2021，Vol.19Issue(4)：335-349,15.

电子科技学刊2021，Vol.19Issue(4)：335-349,15.DOI:10.1016/j.jnlest.2021.100121

Large-Capacity and High-Speed Instruction Cache Based on Divide-by-2 Memory Banks

Qing-Qing Li ¹Zhi-Guo Yu ¹Yi Sun ¹Jing-He Wei ²Xiao-Feng Gu¹

作者信息

1. Engineering Research Center of IoT Technology Applications (Ministry of Education), Jiangnan University, Wuxi 214122
2. No. 58 Research Institute, China Electronics Technology Group Corporation, Wuxi 214035
折叠

摘要

关键词

Cache capacity expansion/divide-by-2 frequency/instruction cache (ICache)/inversed clock

Key words

Cache capacity expansion/divide-by-2 frequency/instruction cache (ICache)/inversed clock

引用本文复制引用

Qing-Qing Li,Zhi-Guo Yu,Yi Sun,Jing-He Wei,Xiao-Feng Gu..Large-Capacity and High-Speed Instruction Cache Based on Divide-by-2 Memory Banks[J].电子科技学刊,2021,19(4):335-349,15.

基金项目

This work was supported by the Postgraduate Research Innovation Program of Jiangsu Province under Grant No. KYCX20_1936 （）

the Fundamental Research Funds for the Central Universities under Grant No. JUSRP51510 （）

the Key Research and Development Program of Jiangsu under Grant No. BE2019003-2. （）

电子科技学刊

OACSCD

ISSN：1674-862X

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