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A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

Quan Pan Xiongshi Luo Zhenghao Li Zhengzhe Jia Fuzhan Chen Xuewei Ding C.Patrick Yue

半导体学报（英文版）2022，Vol.43Issue(7)：71-80,10.
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半导体学报（英文版）2022，Vol.43Issue(7)：71-80,10.DOI:10.1088/1674-4926/43/7/072401

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

Quan Pan 1Xiongshi Luo 1Zhenghao Li 1Zhengzhe Jia 1Fuzhan Chen 1Xuewei Ding 2C.Patrick Yue3

作者信息

  • 1. School of Microelectronics,Engineering Research Center of Integrated Circuits for Next-Generation Communications,Ministry of Education,Southern University of Science and Technology,Shenzhen 518055,China
  • 2. Department of Electronic and Computer Engineering,Hong Kong University of Science and Technology,Hong Kong SAR,China
  • 3. ZTE Microelectronics,Shenzhen 518055,China
  • 折叠

摘要

关键词

clock and data recovery/equalizer/optical receiver/transimpedance amplifier/variable-gain amplifier

Key words

clock and data recovery/equalizer/optical receiver/transimpedance amplifier/variable-gain amplifier

引用本文复制引用

Quan Pan,Xiongshi Luo,Zhenghao Li,Zhengzhe Jia,Fuzhan Chen,Xuewei Ding,C.Patrick Yue..A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS[J].半导体学报（英文版）,2022,43(7):71-80,10.

基金项目

This work was supported in part by Research and Develop-ment Program in Key Areas of Guangdong Province under Grant 2019B010116002,in part by the National Natural Sci-ence Foundation of China under Grant 62074074,and in part by the Science and Technology Plan of Shenzhen under Gr-ants JCYJ20190809142017428 and JCYJ20200109141225025. （）

半导体学报（英文版）

OACSCDCSTPCDEI

1674-4926

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