哈尔滨工业大学学报（英文版）2022，Vol.29Issue(4)：70-80,11.
Analytical Modeling for Translating Statistical Changes to Circuit Variability by Ultra-Deep Submicron Digital Circuit Design
Analytical Modeling for Translating Statistical Changes to Circuit Variability by Ultra?Deep Submicron Digital Circuit Design
Shruti Kalra 1Ruby Beniwal1
作者信息
- 1. Department of Electronics and Communication,Jaypee Institute of Information Technology,Noida 201307,India
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摘要
Abstract
This paper presents a physics?based compact gate delay model that includes all short?channelphenomena prevalent at the ultra?deep submicron technology node of 32 nm. To simplify calculations, the proposed model is connected to a compactα?power law?based ( Sakurai?Newton) model. The model has been tested on a wide range of supply voltages. The model accurately predicts nominal delays and the delays under process variations. It has been shown that at lower technology nodes, the delay is more sensitive to threshold voltage variations, specifically at the sub?threshold operating region as compared with effective channel length variations above the threshold region.关键词
statistical variation/analytical model/process variability/nanoscale CMOS/propagation delayKey words
statistical variation/analytical model/process variability/nanoscale CMOS/propagation delay分类
数理科学引用本文复制引用
Shruti Kalra,Ruby Beniwal..Analytical Modeling for Translating Statistical Changes to Circuit Variability by Ultra-Deep Submicron Digital Circuit Design[J].哈尔滨工业大学学报（英文版）,2022,29(4):70-80,11.
