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FPGA-based acceleration for binary neural networks in edge computing

Jin-Yu Zhan An-Tai Yu Wei Jiang Yong-Jia Yang Xiao-Na Xie Zheng-Wei Chang Jun-Huan Yang

电子科技学刊2023，Vol.21Issue(2)：65-77,13.

电子科技学刊2023，Vol.21Issue(2)：65-77,13.DOI:10.1016/j.jnlest.2023.100204

FPGA-based acceleration for binary neural networks in edge computing

Jin-Yu Zhan ¹An-Tai Yu ¹Wei Jiang ¹Yong-Jia Yang ¹Xiao-Na Xie ²Zheng-Wei Chang ³Jun-Huan Yang⁴

作者信息

1. School of Information and Software Engineering,University of Electronic Science and Technology of China,Chengdu,610054,China
2. School of Automation,Chengdu University of Information Technology,Chengdu,610225,China
3. State Grid Sichuan Electric Power Research Institute,Chengdu,610095,China
4. Department of Information Sciences and Technology,George Mason University,Fairfax,VA22030,USA
折叠

摘要

关键词

Accelerator/Binarization/Field-programmable gate array(FPGA)/Neural networks/Quantification

Key words

Accelerator/Binarization/Field-programmable gate array(FPGA)/Neural networks/Quantification

引用本文复制引用

Jin-Yu Zhan,An-Tai Yu,Wei Jiang,Yong-Jia Yang,Xiao-Na Xie,Zheng-Wei Chang,Jun-Huan Yang..FPGA-based acceleration for binary neural networks in edge computing[J].电子科技学刊,2023,21(2):65-77,13.

基金项目

This work was supported by the Natural Science Foundation of Sichuan Province of China under Grant No.2022NSFSC0500 （）

the National Natural Science Foundation of China under Grant No.62072076. （）

电子科技学刊

OACSCD

ISSN：1674-862X

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