现代雷达2023，Vol.45Issue(7)：75-82,8.DOI:10.16592/j.cnki.1004-7859.2023.07.014
基于SystemVerilog的浮点数约束生成器的研究与实现
A Study and Implementation of a Floating-point Constraint Generator Based on SystemVerilog
吴沁文 1王珊珊1
作者信息
- 1. 南京电子技术研究所,江苏南京210039
- 折叠
摘要
Abstract
SystemVerilog is a specialized language for FPGA verification,and its constrained random mechanism is the kernel to support FPGA random test.However,the SystemVerilog language only provides a constrained randomization mechanism for integral data types,which greatly limits the verification when floating-point random stimulus is needed.In this article,a floating-point con-straint generator based on SystemVerilog is designed.It realizes the generation of constrained random floating-point number through a conversion mechanism,and thus extends the SystemVerilog constrained random mechanism to floating-point data types,which ef-fectively expands the support range of SystemVerilog for constrained random test.关键词
SystemVerilog语言/FPGA验证/约束随机/浮点数Key words
SystemVerilog/FPGA validation/constraint random/floating-point number分类
信息技术与安全科学引用本文复制引用
吴沁文,王珊珊..基于SystemVerilog的浮点数约束生成器的研究与实现[J].现代雷达,2023,45(7):75-82,8.
