基于SystemVerilog的浮点数约束生成器的研究与实现OA北大核心CSCDCSTPCD
A Study and Implementation of a Floating-point Constraint Generator Based on SystemVerilog
SystemVerilog是专用于FPGA验证的语言,它的约束随机机制是支持FPGA随机测试的关键.然而,SystemVerilog语言仅提供了对整数类型的约束随机机制,这大大限制了需要使用浮点数随机激励的验证.文中设计了一种基于System-Verilog 的浮点数约束生成器,它通过转换机制,实现对浮点数的约束随机生成,从而将SystemVerilog的约束随机机制扩大到浮点数据类型,有效扩大了 SystemVerilog约束随机验证的支持范围.
SystemVerilog is a specialized language for FPGA verification,and its constrained random mechanism is the kernel to support FPGA random test.However,the SystemVerilog language only provides a constrained randomization mechanism for integral data types,which greatly limits the verification when floating-point random stimulus is needed.In this article,a floating-point con-straint generator based on SystemVerilog is designed.It realizes the generation of constr…查看全部>>
吴沁文;王珊珊
南京电子技术研究所,江苏南京210039南京电子技术研究所,江苏南京210039
电子信息工程
SystemVerilog语言FPGA验证约束随机浮点数
SystemVerilogFPGA validationconstraint randomfloating-point number
《现代雷达》 2023 (7)
75-82,8
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