首页|期刊导航|半导体学报（英文版）|Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design
半导体学报（英文版）2023，Vol.44Issue(11)：100-112,13.DOI:10.1088/1674-4926/44/11/114103
Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design
Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design
摘要
关键词
short channel effects (SCEs)/junctionless FinFET/analog and RF parameters/SiGeKey words
short channel effects (SCEs)/junctionless FinFET/analog and RF parameters/SiGe引用本文复制引用
Devenderpal Singh,Shalini Chaudhary,Basudha Dewan,Menka Yadav..Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design[J].半导体学报（英文版）,2023,44(11):100-112,13.基金项目
The authors thank the Electronics and Communication Engineering Department,Malaviya National Institute of Tech-nology,Jaipur,for providing essential support to carry out the research work. （）
