高技术通讯2023，Vol.33Issue(11)：1123-1135,13.DOI:10.3772/j.issn.1002-0470.2023.11.001
基于FPGA的软硬件协同的多表哈希连接加速器
FPGA-based accelerator by software-hardware co-design for multi Hash join
摘要
Abstract
It is hard to implement multi-table Hash join on hardware accelerators.On one hand,multi-table join has an indefinite number of tables and various connection modes.The flexibility in multi-table Hash join is in contradiction with fixed hardware architectures.On the other hand,the capacity of intermediate results expands with the number of tables increasing.The capability of data management and monitoring asks for higher hardware overhead.To ena-ble flexible and efficient multi-table Hash join,a software-hardware co-optimization methodology is proposed.Soft-ware subsystem abstracts multi-table Hash join into forward and reverse computation modes,and agilely organizes Hash join processes.Additionally,the memory access and computing are collaboratively optimized in hardware de-sign.A regular hardware Hash table is designed to improve memory bandwidth.Meanwhile,a homogeneous com-puting engine is designed to perform both forward and reverse computation.To further improve the efficiency of Hash join,multi data channels and an instruction control system are configured.The experiment results showed that a single computing engine could improve the performance of multi-table Hash join 9.2-11.0 times higher than con-tral processing unit(CPU).Furthermore,the 8-way parallel multi-table Hash join engines could make full use of DDR bandwidth resources and get 71.1 times performance of CPU.关键词
现场可编程门阵列(FPGA)/多表连接/哈希连接/软硬件协同Key words
field programmable gate array(FPGA)/multi-table join/Hash join/hardware-software co-design引用本文复制引用
吴婧雅,卢文岩,鄢贵海,李晓维..基于FPGA的软硬件协同的多表哈希连接加速器[J].高技术通讯,2023,33(11):1123-1135,13.基金项目
国家自然科学基金(61572470,62002340,61872336)和中国科学院大学青促会基金项目(Y404441000)资助. （61572470,62002340,61872336）
