高技术通讯2023，Vol.33Issue(11)：1146-1159,14.DOI:10.3772/j.issn.1002-0470.2023.11.003
MRC:谐振时钟数字集成全局功耗优化方法
MRC:global power optimization method of resonant clock for digital integration
摘要
Abstract
Aiming at the digital implementation of resonant clock network in the integrated circuit design,this paper pro-poses a modeling and optimization method of resonant clock circuits(MRC),which simplifies the integration process of resonant clock networks.At present,traditional simulation tools for building resonant circuit models is time consuming,and the existing resonant circuit models cannot meet the requirements of rapid implementation and digital library construction.According to the three-stage circuit state of the resonant designs,the polyline reduction model in this paper can obtain the current waveforms of various resonant circuits quickly and accurately.An optimi-zation objective function of global power consumption is also given based on this model,providing a theoretical basis for the selection of circuit parameters.The post-Spice simulation results based on 12 nm Fin-FET technology show that the model accuracy is more than 90%and can accurately fit the actual power consumption trend.Matlab-based implementation of the proposed model can achieve 105 times speedup compared with Spice-based simulation.关键词
谐振时钟/低功耗设计/功耗模型/设计方法学/大规模集成电路时钟设计Key words
resonant clock/low-power design/power model/design methodology/very-large-scale integra-tion clock design引用本文复制引用
贾柯,杨梁,王剑..MRC:谐振时钟数字集成全局功耗优化方法[J].高技术通讯,2023,33(11):1146-1159,14.基金项目
中国科学院战略性先导科技专项(XDC05020100)资助项目. （XDC05020100）
