计算机工程2023，Vol.49Issue(12)：1-9,9.DOI:10.19678/j.issn.1000-3428.0066701
混合精度频域卷积神经网络FPGA加速器设计
FPGA Accelerator Design for Hybrid Precision Frequency Domain Convolutional Neural Network
摘要
Abstract
Deep Convolutional Neural Network(CNN)have large models and high computational complexity,making their deployment in Programmable Gate Array(FPGA)with limited hardware resources difficult.Hybrid precision CNNs can provide an effective trade-off between model size and accuracy,thus providing an efficient solution for reducing the model's memory footprint.As a fast algorithm,the Fast Fourier Transform(FFT)can convert traditional spatial domain CNNs into the frequency domain,effectively reducing the computational complexity of the model.This study presents an FPGA-based accelerator design for 8 bit and 16 bit hybrid precision frequency domain CNNs that supports the dynamic configuration of 8 bit and 16 bit frequency domain convolutions and can pack 8 bit frequency domain multiplication operations to enable the reuse of DSPs for performance improvement.A DSP-based Frequency-domain Processing Element(FPE)is designed to support 8 bit and 16 bit frequency domain convolution operations.It can pack a couple of 8 bit frequency domain multiplications to reuse DSPs to boost throughput.In addition,a mapping dataflow that supports both 8 bit and 16 bit computation patterns and can maximize the reduction of redundant data processing and data movement through data reuse is proposed.The proposed accelerator is evaluated based on the ResNet-18 and VGG16 models using the ImageNet dataset.The experimental results reveal that the proposed model can achieve 29.74 and 56.73 energy efficiency ratio(ratio of GOP to energy consumption)on the ResNet-18 and VGG16 models,respectively,which is 1.2-6.0 times better than those of frequency domain FPGA accelerators.关键词
卷积神经网络/硬件加速器/频域/混合精度/现场可编程门阵列Key words
Convolutional Neural Network(CNN)/hardware accelerator/frequency domain/hybrid precision/Field Programmable Gate Array(FPGA)分类
信息技术与安全科学引用本文复制引用
陈逸,刘博生,徐永祺,武继刚..混合精度频域卷积神经网络FPGA加速器设计[J].计算机工程,2023,49(12):1-9,9.基金项目
国家自然科学基金(62072118). （62072118）
