计算机工程与科学2023，Vol.45Issue(12)：2113-2120,8.DOI:10.3969/j.issn.1007-130X.2023.12.003
基于RISC-V的图卷积神经网络加速器设计
RISC-V based design of graph convolutional neural network accelerator
周理 1赵祉乔 1潘国腾 1铁俊波 1赵王1
作者信息
- 1. 国防科技大学计算机学院,湖南 长沙 410073
- 折叠
摘要
Abstract
Graph Convolutional Networks(GCN),an algorithm for processing non-Euclidean data,is currently mainly implemented on deep learning frameworks such as PyTorch for GPU acceleration.GCN's computation process involves nested matrix multiplication and data access operations,which can be satisfied by GPU in real-time but have high deployment costs and low energy efficiency.To improve the computational performance of GCN algorithm while maintaining software flexibility,this paper pro-poses a custom GCN accelerator based on RSIC-V SoC,which extends the dot product operation and hardware accelerator through hardware-software co-design in the hummingbird E203 SoC platform.The neural network parameter analysis determines the hardware quantization scheme from floating point to 32-bit fixed point.Experimental results show that the proposed accelerator has no accuracy loss and can achieve a maximum speedup of 6.88 times when running GCN algorithm on Cora dataset.关键词
RISC-V/图卷积神经网络/硬件加速器/指令集Key words
RISC-V/graph convolutional neural network/hardware accelerator/instruction set分类
信息技术与安全科学引用本文复制引用
周理,赵祉乔,潘国腾,铁俊波,赵王..基于RISC-V的图卷积神经网络加速器设计[J].计算机工程与科学,2023,45(12):2113-2120,8.
