电子学报2023，Vol.51Issue(10)：2791-2800,10.DOI:10.12263/DZXB.20220932
一种基于有限脉冲响应滤波器的时钟倍频器设计
A Design of Clock Frequency Multiplication Circuit Based on Finite Impulse Response Filter
摘要
Abstract
This paper presents a clock multiplication and jitter reduction circuit based on finite impulse response(FIR)filters.Compared with phase-locked loop(PLL)or delay-locked loop(DLL)techniques used in conventional clock multiplier,the proposed clock multiplier generates a high-precision clock phase based on the working principle of FIR filter while reducing the clock frequency jitter.A new zero-crossing detection circuit is also designed to generate output clock pulses.The proposed clock multiplier can achieve fast lock-in time,as well as low power consumption and area cost.This design is implemented in SMIC 0.18 um CMOS process,the input clock frequency is 32 MHz,the output is multiplied by 5 when the lock-in time is less than 1.5 clock cycles,and the input clock jitter is reduced from 43.6 ps RMS to 24.6 ps RMS.关键词
时钟/倍频器/有限脉冲响应/过零检测/抖动Key words
clock/frequency multiplier/finite impulse response/zero-crossing detection/jitter分类
信息技术与安全科学引用本文复制引用
曾兆权,旭阳欣,马丁·马林森,张岭,张宁..一种基于有限脉冲响应滤波器的时钟倍频器设计[J].电子学报,2023,51(10):2791-2800,10.基金项目
石河子大学国际科技合作推进计划项目(No.GJHZ202106)International Science and Technology Cooperation Promotion Plan Project of Shihezi Uni-versity(No.GJHZ202106) （No.GJHZ202106）
