密码学报2023，Vol.10Issue(6)：1225-1240,16.DOI:10.13868/j.cnki.jcr.000664
面向典型处理器架构的代码级侧信道仿真特性研究
On Simulation Characteristics of Code-Level Side Channel for Typical Processor Architecture
摘要
Abstract
In order to solve the problems of traditional side-channel analysis relying on hardware acquisition equipment and late detection process,the code-level side-channel simulation analysis tech-nology is studied.The code execution is simulated by monitoring and recording the memory address and register value of the cryptographic software code during the operation of the processor.Leaks may occur during the process of code execution.Based on the known research results,this paper expands the mainstream processor architectures such as X86,ARM,SPARC,PowerPC and MIPS,carries out cross-platform register simulation power acquisition and side channel analysis for the open source implementation of AES-128 using cross-compilation and processor virtualization technology,explores and compares the characteristics of code-level side channel simulation under different pro-cessor architectures.Experiments show that,X86(rax/rcx/rdx),ARM(r1/r2/r3),MIPS(v0/v1),PowerPC(r8/r9/r10),SPARC(g1/g2/g3)registers have power leakage caused by data copy and XOR operation.Because of the difference between the simple instruction set and the complex instruction set,the difference feature of leakage is presented.Finally,the register leakage is classified according to the function of source code,so as to verify the applicability of code-level side channel simulation on a variety of processor architectures.关键词
代码级侧信道/处理器架构/软件功耗仿真Key words
code-level side channel analysis/CPU architecture/software power side-channel simu-lation分类
信息技术与安全科学引用本文复制引用
杨光,李东方,沈炜,王纪,刘诗宇..面向典型处理器架构的代码级侧信道仿真特性研究[J].密码学报,2023,10(6):1225-1240,16.基金项目
国防基础科研计划(XX2020204B028)Defense Industrial Technology Development Program of China(XX2020204B028) （XX2020204B028）
