计算机应用研究2024，Vol.41Issue(1)：260-265,6.DOI:10.19734/j.issn.1001-3695.2023.04.0190
基于FPGA的TANGRAM分组密码算法实现
Implementation of TANGRAM block cipher algorithm based on FPGA
摘要
Abstract
TANGRAM block cipher algorithm employs a bit-slice approach and is compatible with multiple software and hard-ware platforms.In response to TANGRAM-128/128 algorithm,this paper proposed a design plan which used Verilog HDL for FPGA implementation.This paper firstly provided an introduction to the characteristics and processed of TANGRAM algorithm and presented a scheme for reducing resource consumption using a finite-state machine for 44 rounds of encryption and decryp-tion computation.Secondly,the engineering implementation of the FPGA algorithm was completed by the domestic Gaoyun plat-form and subjected to functional simulation and data correctness validation.Furthermore,relevant tests were performed on Quar-tus Ⅱ 13.1.0 platform for comparison.Test results show that,based on Cyclone Ⅳ E EP4CE40F29C6 chip from Altera,TAN-GRAM block cipher algorithm has a maximum clock frequency of 138.64 MHz and an encryption/decryption speed of 403.30 Mbps.While based on the GW2A-55 chip from Gaoyun,the maximum clock frequency is 96.537 MHz and the encryp-tion/decryption speed is 280.80 Mbps.关键词
TANGRAM/分组密码算法/Verilog HDL/有限状态机Key words
TANGRAM/block cipher algorithm/Verilog HDL/finite-state machine分类
信息技术与安全科学引用本文复制引用
王建新,许弘可,郑玉崝,肖超恩,张磊,洪睿鹏..基于FPGA的TANGRAM分组密码算法实现[J].计算机应用研究,2024,41(1):260-265,6.基金项目
教育部新工科研究与实践项目(E-AQGABQ20202704) （E-AQGABQ20202704）
北京高等教育"本科教学改革创新项目"(202110018002) （202110018002）
北京电子科技学院一流学科建设项目(20210064Z0401,20210056Z0402) （20210064Z0401,20210056Z0402）
中央高校基本科研业务费资金资助项目(328202205,328202271,328202269) （328202205,328202271,328202269）
国家重点研发计划基金资助项目(2017YFB0801803) （2017YFB0801803）
