现代信息科技2024，Vol.8Issue(4)：61-65,5.DOI:10.19850/j.cnki.2096-4706.2024.04.013
改进的共享布尔逻辑进位选择加法器设计
Design of an Improved Shared Boolean Logic Carry Select Adder
吴盛林1
作者信息
- 1. 安徽理工大学 计算机科学与工程学院,安徽 淮南 232001
- 折叠
摘要
Abstract
In today's highly digitized and computationally intensive environment,it is crucial to design high-speed and low-power adders,such as Carry Select Adders(CSLA).Based on this,an improved shared Boolean logic Carry Select Adder is proposed.Compared to existing designs,this design reduces the number of transistors on the basis of sacrificing some power consumption and speed.This design utilizes TSMC65 nm technology to achieve 4-bit design in Cadence.The simulation results show that compared to the Fast Adder Module-2(FAM2)Carry Select Adder,this scheme reduces the number of transistors,power consumption,and power consumption delay product by 8.91％,8.13％,and 6.02％,respectively.关键词
进位选择加法器/晶体管数量/功耗/延迟Key words
Carry Select Adder/the number of transistors/power consumption/delay分类
信息技术与安全科学引用本文复制引用
吴盛林..改进的共享布尔逻辑进位选择加法器设计[J].现代信息科技,2024,8(4):61-65,5.
