计算机与数字工程2023，Vol.51Issue(11)：2524-2530,7.DOI:10.3969/j.issn.1672-9722.2023.11.010
低延迟抖动的证券行情数据解析系统设计与实现
Design and Implementation of a Securities Market Data Analysis System with Low Latency Jitter
摘要
Abstract
In order to solve the problems of high delay,high jitter,easy blockage,hashing conflict and high maintenance cost in the process of analysis and processing of stock market data by pure software,a cooperative development mode based on OpenCL and HLS is proposed.In Xilinx Alevo U50 FPGA accelerator card,low delay and low jitter are realized by HLS instruction level par-allel flow optimization to improve parallelism,KVS storage optimization to reduce hash conflict,binary search parallel optimization to reduce delay,and dynamic key-value table storage to improve storage utilization.The experiment shows that,compared with CPU I9-9900X 10C20T,the analysis speed is increased by 8 times,the analysis time of single market data is controlled at 189.8ns,and the jitter amplitude is maintained within 14ns.Compared with traditional HDL hardware FPGA development mode,the development efficiency is improved by 3～4 times.It can better adapt to the iterative needs of the financial market.关键词
金融/低延迟低抖动/行情数据解析/高层次综合/现场可编程门阵列Key words
financial/low latency low jitter/market data analysis/high level synthesis/field programmable gate array分类
管理科学引用本文复制引用
丁楠,柴志雷,高昊晖,冯一飞,张曦煌..低延迟抖动的证券行情数据解析系统设计与实现[J].计算机与数字工程,2023,51(11):2524-2530,7.基金项目
国家自然科学基金项目(编号:61972180)资助. （编号:61972180）
