现代电子技术2024，Vol.47Issue(6)：91-96,6.DOI:10.16652/j.issn.1004-373x.2024.06.015
一种带Cache加速的HyperRAM控制器设计与验证
Design and verification of HyperRAM controller with Cache acceleration
邹敏 1鲁澳宇 1邹望辉 1喻华2
作者信息
- 1. 长沙理工大学 物理与电子科学学院, 湖南 长沙 410114
- 2. 广东华芯微特集成电路有限公司, 湖南 长沙 410205
- 折叠
摘要
Abstract
In allusion to the problems of high-performance requirements,small size and low power consumption of storage devices in wearable devices,a scalable high-performance HyperRAM controller is implemented on FPGA,and the design of Cache acceleration is introduced to improve the hit rate of frequently accessed data and optimize the memory access mode,so as to realize higher-speed data transmission and optimized system performance.By means of UVM verification methodology and FPGA verification,the results show that in comparison with ordinary HyperRAM,the performance of the HyperRAM controller with Cache cache is improved by 61%when reading and writing continuous addresses,and has good reliability and effectiveness,which can provide an efficient and flexible memory solution for embedded systems.关键词
HyperRAM控制器/Cache缓存/可穿戴设备/存储器/UVM验证方法学/FPGAKey words
HyperRAM controller/Cache cache/wearable devices/memory/UVM validation methodology/FPGA分类
电子信息工程引用本文复制引用
邹敏,鲁澳宇,邹望辉,喻华..一种带Cache加速的HyperRAM控制器设计与验证[J].现代电子技术,2024,47(6):91-96,6.
