一种带Cache加速的HyperRAM控制器设计与验证OACSTPCD

In allusion to the problems of high-performance requirements,small size and low power consumption of storage devices in wearable devices,a scalable high-performance HyperRAM controller is implemented on FPGA,and the design of Cache acceleration is introduced to improve the hit rate of frequently accessed data and optimize the memory access mode,so as to realize higher-speed data transmission and optimized system performance.By means of UVM verification methodology and FPGA verification,the results show that in comparison with ordinary HyperRAM,the performance of the HyperRAM controller with Cache cache is improved by 61%when reading and writing continuous addresses,and has good reliability and effectiveness,which can provide an efficient and flexible memory solution for embedded systems.