电子器件2024，Vol.47Issue(1)：48-54,7.DOI:10.3969/j.issn.1005-9490.2024.01.009
面向微控制器的卷积神经网络加速器设计
Design of Convolutional Neural Network Accelerator for Microcontroller
摘要
Abstract
Aiming at the problem that the performance of embedded microcontroller is difficult to meet the task of real-time image recog-nition,a convolutional neural network accelerator suitable for microcontroller is proposed.The accelerator has a non blocking row paral-lel multiplier adder unit structure in the convolutional layer.It has higher hardware utilization.In order to meet the throughput of row parallel data,a special convolution SRAM memory is designed.The accelerator integrates pooling and activation units into the data path,effectively reducing the time overhead caused by repeated data access.Through FPGA prototype verification,the performance of the accelerator can reach 92.2 GOPS@100 MHz.The accelerator is synthesized based on TSMC 130 nm process.The dynamic power consumption of the accelerator is 33 mW,the area is 90 764.2 μm2,and the energy efficiency ratio is 2 793 GOPS/W,which is about a hundred times higher than that of FPGA accelerator.The accelerator has the characteristics of low power and cost,which is conducive to the wide application of embedded systems in the field of machine vision,such as object detection,face recognition and so on.关键词
卷积神经网络/并行计算/流水线/硬件加速器/专用集成电路Key words
convolutional neural network/parallel computing/pipeline/hardware accelerator/application specific integrated circuit分类
信息技术与安全科学引用本文复制引用
乔建华,吴言,栗亚宁,雷光政..面向微控制器的卷积神经网络加速器设计[J].电子器件,2024,47(1):48-54,7.基金项目
山西省研究生教育改革研究课题项目(2021YJJG247) （2021YJJG247）
